`timescale 1ns / 1ps


module top();

reg enc;
reg rst;
wire rst_sync;

CLOCK_SYNC clk_sync(
		.clk_ENC(enc),
		.rst(rst),
		.rst_sync(rst_sync)
	);

initial begin
	$dumpfile("wave.vcd");
	$dumpvars(0,top);
end

initial begin
	// rst = 0;
	enc = 0;
	forever #100 enc = ~enc;
end

initial begin
	#50	 rst = 0;
	#215 rst = 1;
	#90 rst = 0;
	#250 rst = 1;
	#203 rst = 0;
	#257 rst = 1;
	#254 rst = 0;
	#1500;
	$finish;
end


endmodule
